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Merge pull request #961 from devnexen/windows_tighten_criterias

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_mi_memcpy/_mi_memzero: tighten criteria for intrinsics for windows.
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Daan 2024-11-25 19:25:26 -08:00 • committed by GitHub
commit cd61eb7cf1
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GPG key ID: B5690EEEBB952194
2 changed files with 7 additions and 3 deletions
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5
include/mimalloc/internal.h
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@ -936,8 +936,9 @@ static inline size_t mi_bsr(uintptr_t x) {
#if !MI_TRACK_ENABLED && defined(_WIN32) && (defined(_M_IX86) || defined(_M_X64)) #if !MI_TRACK_ENABLED && defined(_WIN32) && (defined(_M_IX86) || defined(_M_X64))
#include <intrin.h> #include <intrin.h>
extern bool _mi_cpu_has_fsrm; extern bool _mi_cpu_has_fsrm;
extern bool _mi_cpu_has_erms;
static inline void _mi_memcpy(void* dst, const void* src, size_t n) { static inline void _mi_memcpy(void* dst, const void* src, size_t n) {
if (_mi_cpu_has_fsrm) { if ((_mi_cpu_has_fsrm && n <= 128) || (_mi_cpu_has_erms && n > 128)) {
__movsb((unsigned char*)dst, (const unsigned char*)src, n); __movsb((unsigned char*)dst, (const unsigned char*)src, n);
} }
else { else {
@ -945,7 +946,7 @@ static inline void _mi_memcpy(void* dst, const void* src, size_t n) {
} }
} }
static inline void _mi_memzero(void* dst, size_t n) { static inline void _mi_memzero(void* dst, size_t n) {
if (_mi_cpu_has_fsrm) { if ((_mi_cpu_has_fsrm && n <= 128) || (_mi_cpu_has_erms && n > 128)) {
__stosb((unsigned char*)dst, 0, n); __stosb((unsigned char*)dst, 0, n);
} }
else { else {

5
src/init.c
View file

@ -590,12 +590,15 @@ void _mi_process_load(void) {
#if defined(_WIN32) && (defined(_M_IX86) || defined(_M_X64)) #if defined(_WIN32) && (defined(_M_IX86) || defined(_M_X64))
#include <intrin.h> #include <intrin.h>
mi_decl_cache_align bool _mi_cpu_has_fsrm = false; mi_decl_cache_align bool _mi_cpu_has_fsrm = false;
mi_decl_cache_align bool _mi_cpu_has_erms = false;
static void mi_detect_cpu_features(void) { static void mi_detect_cpu_features(void) {
// FSRM for fast rep movsb support (AMD Zen3+ (~2020) or Intel Ice Lake+ (~2017)) // FSRM for fast short rep movsb/stosb support (AMD Zen3+ (~2020) or Intel Ice Lake+ (~2017))
// EMRS for fast enhanced rep movsb/stosb support
int32_t cpu_info[4]; int32_t cpu_info[4];
__cpuid(cpu_info, 7); __cpuid(cpu_info, 7);
_mi_cpu_has_fsrm = ((cpu_info[3] & (1 << 4)) != 0); // bit 4 of EDX : see <https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features> _mi_cpu_has_fsrm = ((cpu_info[3] & (1 << 4)) != 0); // bit 4 of EDX : see <https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features>
_mi_cpu_has_erms = ((cpu_info[2] & (1 << 9)) != 0); // bit 9 of ECX : see <https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features>
} }
#else #else
static void mi_detect_cpu_features(void) { static void mi_detect_cpu_features(void) {