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Merge branch 'dev' into dev-slice
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commit
78e2e580f8
6 changed files with 30 additions and 21 deletions
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@ -796,21 +796,21 @@ static inline mi_threadid_t _mi_thread_id(void) mi_attr_noexcept {
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}
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#elif defined(__GNUC__) && \
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(defined(__x86_64__) || defined(__i386__) || defined(__arm__) || defined(__aarch64__))
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(defined(__x86_64__) || defined(__i386__) || defined(__aarch64__))
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// TLS register on x86 is in the FS or GS register, see: https://akkadia.org/drepper/tls.pdf
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// see also https://akkadia.org/drepper/tls.pdf for more info on the TLS register.
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static inline void* mi_tls_slot(size_t slot) mi_attr_noexcept {
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void* res;
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const size_t ofs = (slot*sizeof(void*));
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#if defined(__i386__)
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__asm__("movl %%gs:%1, %0" : "=r" (res) : "m" (*((void**)ofs)) : ); // 32-bit always uses GS
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__asm__("movl %%gs:%1, %0" : "=r" (res) : "m" (*((void**)ofs)) : ); // x86 32-bit always uses GS
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#elif defined(__APPLE__) && defined(__x86_64__)
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__asm__("movq %%gs:%1, %0" : "=r" (res) : "m" (*((void**)ofs)) : ); // x86_64 macOSX uses GS
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#elif defined(__x86_64__) && (MI_INTPTR_SIZE==4)
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__asm__("movl %%fs:%1, %0" : "=r" (res) : "m" (*((void**)ofs)) : ); // x32 ABI
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#elif defined(__x86_64__)
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__asm__("movq %%fs:%1, %0" : "=r" (res) : "m" (*((void**)ofs)) : ); // x86_64 Linux, BSD uses FS
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#elif defined(__arm__)
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#elif defined(__arm__) // arm32: defined but currently not used (see issue #495)
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void** tcb; MI_UNUSED(ofs);
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__asm__ volatile ("mrc p15, 0, %0, c13, c0, 3\nbic %0, %0, #3" : "=r" (tcb));
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res = tcb[slot];
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@ -827,7 +827,7 @@ static inline void* mi_tls_slot(size_t slot) mi_attr_noexcept {
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return res;
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}
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// setting is only used on macOSX for now
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// setting a tls slot is only used on macOSX for now
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static inline void mi_tls_slot_set(size_t slot, void* value) mi_attr_noexcept {
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const size_t ofs = (slot*sizeof(void*));
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#if defined(__i386__)
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@ -855,8 +855,8 @@ static inline void mi_tls_slot_set(size_t slot, void* value) mi_attr_noexcept {
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}
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static inline mi_threadid_t _mi_thread_id(void) mi_attr_noexcept {
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#if defined(__arm__) || (defined(__ANDROID__) && defined(__aarch64__))
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// issue #384, #495: on arm32 and arm32/arm64 Android, slot 1 is the thread ID (pointer to pthread internal struct)
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#if defined(__ANDROID__) && (defined(__arm__) || defined(__aarch64__))
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// issue #384, #495: on arm Android, slot 1 is the thread ID (pointer to pthread internal struct)
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return (uintptr_t)mi_tls_slot(1);
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#else
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// in all our other targets, slot 0 is the pointer to the thread control block
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@ -864,7 +864,7 @@ static inline mi_threadid_t _mi_thread_id(void) mi_attr_noexcept {
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#endif
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}
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#else
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// otherwise use standard C
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// otherwise use portable C
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static inline mi_threadid_t _mi_thread_id(void) mi_attr_noexcept {
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return (uintptr_t)&_mi_heap_default;
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}
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@ -164,7 +164,7 @@ typedef int32_t mi_ssize_t;
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#if (MI_MEDIUM_OBJ_WSIZE_MAX >= 655360)
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#error "mimalloc internal: define more bins"
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#endif
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#if (MI_ALIGNED_MAX > MI_SEGMENT_SIZE/2)
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#if (MI_ALIGNMENT_MAX > MI_SEGMENT_SIZE/2)
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#error "mimalloc internal: the max aligned boundary is too large for the segment size"
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#endif
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#if (MI_ALIGNED_MAX % MI_SEGMENT_SLICE_SIZE != 0)
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@ -166,7 +166,7 @@ mi_decl_export void mi_process_info(size_t* elapsed_msecs, size_t* user_msecs, s
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// Note that `alignment` always follows `size` for consistency with unaligned
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// allocation, but unfortunately this differs from `posix_memalign` and `aligned_alloc`.
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// -------------------------------------------------------------------------------------
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#define MI_ALIGNED_MAX (1024*1024UL) // maximum supported alignment is 1MiB
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#define MI_ALIGNMENT_MAX (1024*1024UL) // maximum supported alignment is 1MiB
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mi_decl_nodiscard mi_decl_export mi_decl_restrict void* mi_malloc_aligned(size_t size, size_t alignment) mi_attr_noexcept mi_attr_malloc mi_attr_alloc_size(1) mi_attr_alloc_align(2);
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mi_decl_nodiscard mi_decl_export mi_decl_restrict void* mi_malloc_aligned_at(size_t size, size_t alignment, size_t offset) mi_attr_noexcept mi_attr_malloc mi_attr_alloc_size(1);
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