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fix mi_ctz/clz/bsf/bsr to avoid msvc compilation bug (issue #1071, pr #1081)

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Daan 2025-05-02 08:14:36 -07:00
parent 61f3ffd2a6
commit 3c3d16fe48
1 changed files with 14 additions and 8 deletions
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22
include/mimalloc/bits.h
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@ -236,8 +236,9 @@ static inline size_t mi_ctz(size_t x) {
#elif defined(_MSC_VER) && MI_ARCH_X64 && defined(__BMI1__) #elif defined(_MSC_VER) && MI_ARCH_X64 && defined(__BMI1__)
return (x!=0 ? _tzcnt_u64(x) : MI_SIZE_BITS); // ensure it still works on non-BMI1 cpu's as well return (x!=0 ? _tzcnt_u64(x) : MI_SIZE_BITS); // ensure it still works on non-BMI1 cpu's as well
#elif defined(_MSC_VER) && (MI_ARCH_X64 || MI_ARCH_X86 || MI_ARCH_ARM64 || MI_ARCH_ARM32) #elif defined(_MSC_VER) && (MI_ARCH_X64 || MI_ARCH_X86 || MI_ARCH_ARM64 || MI_ARCH_ARM32)
unsigned long idx; if (x==0) return MI_SIZE_BITS; // test explicitly for `x==0` to avoid codegen bug (issue #1071)
return (mi_msc_builtinz(_BitScanForward)(&idx, x) ? (size_t)idx : MI_SIZE_BITS); unsigned long idx; mi_msc_builtinz(_BitScanForward)(&idx, x);
return (size_t)idx;
#elif defined(__GNUC__) && MI_ARCH_X86 #elif defined(__GNUC__) && MI_ARCH_X86
size_t r = MI_SIZE_BITS; size_t r = MI_SIZE_BITS;
__asm ("bsf\t%1, %0" : "+r"(r) : "r"(x) : "cc"); __asm ("bsf\t%1, %0" : "+r"(r) : "r"(x) : "cc");
@ -260,8 +261,9 @@ static inline size_t mi_clz(size_t x) {
#elif mi_has_builtinz(clz) #elif mi_has_builtinz(clz)
return (x!=0 ? (size_t)mi_builtinz(clz)(x) : MI_SIZE_BITS); return (x!=0 ? (size_t)mi_builtinz(clz)(x) : MI_SIZE_BITS);
#elif defined(_MSC_VER) && (MI_ARCH_X64 || MI_ARCH_X86 || MI_ARCH_ARM64 || MI_ARCH_ARM32) #elif defined(_MSC_VER) && (MI_ARCH_X64 || MI_ARCH_X86 || MI_ARCH_ARM64 || MI_ARCH_ARM32)
unsigned long idx; if (x==0) return MI_SIZE_BITS; // test explicitly for `x==0` to avoid codegen bug (issue #1071)
return (mi_msc_builtinz(_BitScanReverse)(&idx, x) ? MI_SIZE_BITS - 1 - (size_t)idx : MI_SIZE_BITS); unsigned long idx; mi_msc_builtinz(_BitScanReverse)(&idx, x);
return (MI_SIZE_BITS - 1 - (size_t)idx);
#elif defined(__GNUC__) && (MI_ARCH_X64 || MI_ARCH_X86) #elif defined(__GNUC__) && (MI_ARCH_X64 || MI_ARCH_X86)
if (x==0) return MI_SIZE_BITS; if (x==0) return MI_SIZE_BITS;
size_t r; size_t r;
@ -291,8 +293,10 @@ static inline bool mi_bsf(size_t x, size_t* idx) {
__asm ( "tzcnt\t%2, %1" : "=@ccc"(is_zero), "=r"(*idx) : "r"(x) : "cc" ); __asm ( "tzcnt\t%2, %1" : "=@ccc"(is_zero), "=r"(*idx) : "r"(x) : "cc" );
return !is_zero; return !is_zero;
#elif defined(_MSC_VER) && (MI_ARCH_X64 || MI_ARCH_X86 || MI_ARCH_ARM64 || MI_ARCH_ARM32) #elif defined(_MSC_VER) && (MI_ARCH_X64 || MI_ARCH_X86 || MI_ARCH_ARM64 || MI_ARCH_ARM32)
unsigned long i; if (x==0) return false; // test explicitly for `x==0` to avoid codegen bug (issue #1071)
return (mi_msc_builtinz(_BitScanForward)(&i, x) ? (*idx = (size_t)i, true) : false); unsigned long i; mi_msc_builtinz(_BitScanForward)(&i, x);
*idx = (size_t)i;
return true;
#else #else
return (x!=0 ? (*idx = mi_ctz(x), true) : false); return (x!=0 ? (*idx = mi_ctz(x), true) : false);
#endif #endif
@ -303,8 +307,10 @@ static inline bool mi_bsf(size_t x, size_t* idx) {
// with the `idx` is set to the bit index (`0 <= *idx < MI_BFIELD_BITS`). // with the `idx` is set to the bit index (`0 <= *idx < MI_BFIELD_BITS`).
static inline bool mi_bsr(size_t x, size_t* idx) { static inline bool mi_bsr(size_t x, size_t* idx) {
#if defined(_MSC_VER) && (MI_ARCH_X64 || MI_ARCH_X86 || MI_ARCH_ARM64 || MI_ARCH_ARM32) #if defined(_MSC_VER) && (MI_ARCH_X64 || MI_ARCH_X86 || MI_ARCH_ARM64 || MI_ARCH_ARM32)
unsigned long i; if (x==0) return false; // test explicitly for `x==0` to avoid codegen bug (issue #1071)
return (mi_msc_builtinz(_BitScanReverse)(&i, x) ? (*idx = (size_t)i, true) : false); unsigned long i; mi_msc_builtinz(_BitScanReverse)(&i, x);
*idx = (size_t)i;
return true;
#else #else
return (x!=0 ? (*idx = MI_SIZE_BITS - 1 - mi_clz(x), true) : false); return (x!=0 ? (*idx = MI_SIZE_BITS - 1 - mi_clz(x), true) : false);
#endif #endif