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Merge f58d34fe28 into 2e6ab0f230

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Jim Huang 2023-03-13 09:55:05 +09:00 • committed by GitHub
commit 285bc7a5a1
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2 changed files with 48 additions and 1 deletions
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24
CMakeLists.txt
View file

@ -301,6 +301,30 @@ else()
endif() endif()
endif() endif()
# -----------------------------------------------------------------------------
# Cache line size detection
# -----------------------------------------------------------------------------
if (CMAKE_CROSSCOMPILING)
message(STATUS "Cross-compiling - cache line size detection disabled")
else()
if (CMAKE_SYSTEM_PROCESSOR MATCHES "^(aarch64.*|AARCH64.*|arm64.*)")
if (APPLE)
execute_process(COMMAND sysctl -n hw.cachelinesize
OUTPUT_VARIABLE L1_DCACHE_LINE_SIZE
OUTPUT_STRIP_TRAILING_WHITESPACE)
else()
if (${CMAKE_SYSTEM_NAME} STREQUAL "Linux")
execute_process(COMMAND getconf LEVEL1_DCACHE_LINESIZE
OUTPUT_VARIABLE L1_DCACHE_LINE_SIZE
OUTPUT_STRIP_TRAILING_WHITESPACE)
endif()
endif()
endif()
endif()
if (L1_DCACHE_LINE_SIZE)
list(APPEND mi_defines MI_CACHE_LINE=${L1_DCACHE_LINE_SIZE})
endif()
# ----------------------------------------------------------------------------- # -----------------------------------------------------------------------------
# Install and output names # Install and output names
# ----------------------------------------------------------------------------- # -----------------------------------------------------------------------------

25
include/mimalloc-internal.h
View file

@ -17,7 +17,30 @@ terms of the MIT license. A copy of the license can be found in the file
#define mi_trace_message(...) #define mi_trace_message(...)
#endif #endif
#define MI_CACHE_LINE 64 // Determine system L1 cache line size at compile time for purposes of alignment.
#ifndef MI_CACHE_LINE
#if defined(__i386__) || defined(__x86_64__)
#define MI_CACHE_LINE 64
#elif defined(__aarch64__)
// FIXME: read special register ctr_el0 to get L1 dcache size.
#define MI_CACHE_LINE 64
#elif defined(__arm__)
// The cache line sizes for Arm depend on implementations, not architectures.
// There are even implementations with cache line sizes configurable at boot time.
#if __ARM_ARCH__ == 7
#define MI_CACHE_LINE 64
#else
// TODO: list known Arm implementations
#define MI_CACHE_LINE 32
#endif
#endif
#endif
#ifndef MI_CACHE_LINE
// A reasonable default value
#define MI_CACHE_LINE 64
#endif
#if defined(_MSC_VER) #if defined(_MSC_VER)
#pragma warning(disable:4127) // suppress constant conditional warning (due to MI_SECURE paths) #pragma warning(disable:4127) // suppress constant conditional warning (due to MI_SECURE paths)
#pragma warning(disable:26812) // unscoped enum warning #pragma warning(disable:26812) // unscoped enum warning