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Merge f58d34fe28
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285bc7a5a1
2 changed files with 48 additions and 1 deletions
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@ -17,7 +17,30 @@ terms of the MIT license. A copy of the license can be found in the file
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#define mi_trace_message(...)
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#endif
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#define MI_CACHE_LINE 64
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// Determine system L1 cache line size at compile time for purposes of alignment.
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#ifndef MI_CACHE_LINE
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#if defined(__i386__) || defined(__x86_64__)
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#define MI_CACHE_LINE 64
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#elif defined(__aarch64__)
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// FIXME: read special register ctr_el0 to get L1 dcache size.
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#define MI_CACHE_LINE 64
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#elif defined(__arm__)
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// The cache line sizes for Arm depend on implementations, not architectures.
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// There are even implementations with cache line sizes configurable at boot time.
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#if __ARM_ARCH__ == 7
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#define MI_CACHE_LINE 64
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#else
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// TODO: list known Arm implementations
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#define MI_CACHE_LINE 32
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#endif
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#endif
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#endif
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#ifndef MI_CACHE_LINE
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// A reasonable default value
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#define MI_CACHE_LINE 64
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#endif
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#if defined(_MSC_VER)
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#pragma warning(disable:4127) // suppress constant conditional warning (due to MI_SECURE paths)
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#pragma warning(disable:26812) // unscoped enum warning
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